| | Preliminary Program
| 08:45 - 08:50 | Welcome Remarks | | 08:50 - 09:40 | Keynote talk I: Accelerating Data Center Applications using Reconfigurable Logic |
| Derek Chiou, University of Texas at Austin/Microsoft |
| Abstract: Data centers are a highly competitive environment that demands high performance and energy efficiency and, in many cases, low latency. Custom hardware can provide significant improvements over conventional microprocessors on those metrics. Microsoft has been investigating the use of reconfigurable logic, in the form of field programmable gate arrays, to accelerate our data centers. In this talk, I will describe some of our efforts in this area.
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| Bio: Derek Chiou is a Principal Architect at Microsoft where he co-leads a team working on FPGAs for data center applications and an associate professor at The University of Texas at Austin. His research areas are FPGA acceleration, high performance computer simulation, rapid system design, computer architecture, parallel computing, Internet router architecture, and network processors. Before going to UT, he was a system architect and lead the performance modeling team at Avici Systems, a manufacturer of terabit core routers. Derek received his Ph.D., S.M. and S.B. degrees in Electrical Engineering and Computer Science from MIT.
| | 09:40 - 10:15 | Invited Talk: Platform for Accelerating Big Data Analytics |
| Norbert Egi, Huawei Technologies |
| Abstract: Datacenter technology has been evolving to address the constantly increasing demands of applications as well as that of datacenter operators aiming for high performance, cost and power efficiency as well as improved reliability. In this talk, we discuss how recent architectural changes at the chip, server and datacenter level have influenced the creation of a novel hardware platform closely integrating analytics with storage and utilizing on numerous technological advances to achieve industry leading SQL query execution performance on big data. The above mentioned platform incorporates numerous performance boosting hardware and software techniques while in the same time increases the overall cost-efficiency of the system.
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| Bio: Norbert Egi is a Staff Researcher in the IT Research Department at Huawei Technologies. His expertise lies in system architectures in compute, network as well as storage systems. He is currently focusing on accelerating big data query execution and amongst others has previously worked on cost-efficient micro-servers and data center infrastructure virtualization. He has co-authored numerous patents and has published research papers in highly ranked conferences (i.e. NSDI, OSDI, SOSP, ACM HotNets, CoNext, etc.).
| | 10:15 - 10:35 | Coffee Break | | 10:35 - 12:00 | Accelerating Big Data Processing (Session 1) |
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TimeThief: Leveraging Network Variability to Save Datacenter Energy in On-line Data-Intensive Applications
Balajee Vamanan (Purdue University )
Hamza Bin Sohail (Purdue University )
Jahangir Hasan (Google Inc.)
T.N. Vijaykumar (Purdue University ) ASBD_2015_submission_4.pdf
CoDEN: A Hardware/Software CoDesign Emulation Platform for SSD-Accelerated Near Data Processing
Jie Zhang (The University of Texas at Dallas)
Damian Szmulewicz (Texas Instruments)
Erick Macias (Texas Instruments)
Myoungsoo Jung (The University of Texas at Dallas) ASBD_2015_submission_6.pdf
Sort vs. Hash Join Revisited for Near-Data Execution
Nooshin S. Mirzadeh (EcoCloud, EPFL)
Onur Kocberber (EcoCloud, EPFL)
Babak Falsafi (EcoCloud, EPFL)
Boris Grot (University of Edinburgh) ASBD_2015_submission_3.pdf
| | 12:00 - 13:10 | Lunch Time
| | 13:10 - 13:50 | Keynote talk II: Processing near memory for data-intensive workloads |
| Nuwan Jayasena, Advanced Micro Devices Inc |
| Abstract: As power and thermal concerns become key limiters of computing performance, reducing the overhead of moving data to and from processor cores becomes increasingly important. Processing near memory (PNM) is a promising approach for reducing data movement and for significantly improving energy efficiency for data-intensive workloads. A confluence of industry trends, from execution architectures and memory interfaces to packaging technologies and programming abstractions, is making PNM commercially viable in the near future. This talk describes an approach to PNM that builds on modest evolutions of technologies that are already available. Many architectural decisions are driven by ease-of-programming considerations with the aim of making PNM broadly applicable. Early evaluations confirm the anticipated energy efficiency improvements across a wide range of applications. This talk also highlights some of the areas that must be addressed by the research community in order to fully realize the potential of PNM.
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| Bio: Nuwan Jayasena is a Principal Member of Technical Staff at Advanced Micro Devices Inc., where he leads research efforts on processing near memory and multi-level memories. His interests include memory systems, heterogeneous computing, processor microarchitecture, and emerging technologies and applications. Prior to AMD, Nuwan was a processor architect at Stream Processors Inc. and at Nvidia Corp. He has a PhD in electrical engineering from Stanford University.
| | 13:50 - 14:50 | Automata for Big Data (Session 2) |
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Entity Resolution Acceleration using Automata Processor
Chunkun Bo(University of Virginia)
Ke Wang (University of Virginia)
Kevin Skadron (University of Virginia)
Jeffery Fox (University of Virginia) ASBD_2015_submission_2.pdf
Nondeterministic Finite Automata in Hardware - the Case of the Levenshtein Automaton
Tommy Tracy II (University of Virginia)
Mircea Stan (University of Virginia)
Nathan Brunell (University of Virginia)
Jack Wadden (University of Virginia)
Ke Wang (University of Virginia)
Kevin Skadron (University of Virginia)
Gabriel Robins (University of Virginia) ASBD_2015_submission_5.pdf
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Committees
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Workshop Co-Organizers:
Lixin Zhang, ICT/CAS China
Program Co-Chairs:
Yungang Bao, ICT/CAS China
Boris Grot, University of Edinburgh
Program Committee:
Rajeev Balasubramonian, University of Utah
Arka Basu, AMD
Yunji Chen, ICT
Eric Chung, Microsoft
Babak Falsafi, EPFL
Paolo Faraboschi, HP Labs
Mike Ferdman, Stony Brook University
John Kim, KAIST
Chao Li, Shanghai Jiao Tong University
Tao Li, University of Florida
David Meisner, Facebook
Lingjia Tang, University of Michigan
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Steering Committee:
Jian Li, Huawei
Jichuan Chang, Google
Evan Speight, IBM Research
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Call for papers
The term "Big Data" refers to the continuing massive expansion in the data volume and diversity as well as the speed and complexity of data processing. The use of big data underpins critical activities in all sectors of our society. Achieving the full transformative potential of big data in this increasingly digital world requires both new data analysis algorithms and a new class of systems to handle the dramatic data growth, the demand to integrate structured and unstructured data analytics, and the increasing computing needs of massive-scale analytics.
We are pleased to request papers for presentation at the upcoming Fifth Workshop on Architectures and Systems for Big Data (ASBD 2015) held in conjunction with ISCA-42. The workshop will provide a forum to exchange research ideas related to all critical aspects of emerging analytics systems for big data, including architectural support, benchmarks and metrics, data management software, operating systems, and emerging challenges and opportunities. We hope to attract a group of interdisciplinary researchers from academia, industry and government research labs. To encourage discussion between participants, the workshop will include significant time for interactions between the presenters and the audience. We also plan to have a keynote speaker and/or panel session.
Topics of interest include but are not limited to:
Processor, memory and system architectures for data analytics Benchmarks, metrics and workload characterization for big data Accelerators for analytics and data-intensive computing Implications of data analytics to mobile and embedded systems Energy efficiency and energy-efficient designs for analytics Availability, fault tolerance and data recovery in big data environments Scalable system and network designs for high concurrency/bandwidth streaming Data management and analytics for vast amounts of unstructured data Evaluation tools, methodologies and workload synthesis OS, distributed systems and system management support for large-scale analytics Debugging and performance analysis tools for analytics and big data Programming systems and language support for deep analytics MapReduce and other processing paradigms for analytics
We encourage researchers from all institutions to submit their work for review. Preliminary results of interesting ideas and work-in-progress are welcome. Submissions that are likely to generate vigorous discussion will be favored!
Submission format: All papers should be submitted in PDF format,
using 10 point or larger font for text (8 points or larger for figures and
tables), total length not to exceed 6 pages. Paper Submission : https://www.easychair.org/conferences/?conf=asbd2015
Important Dates
Submissions deadline: March 23, 2015
Submissions deadline: April 10, 2015
Author notification: April 30, 2015
Prior Workshops:
ASBD 2014
ASBD 2013
ASBD 2012
ASBD 2011
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