Biography：
Yinan Xu is an Assistant Professor at the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS). He received his B.Eng. degree from the University of Chinese Academy of Sciences in 2019 and his Ph.D. degree from ICT, CAS in 2025. He is a core developer of the XiangShan open-source high-performance RISC-V processor, where he has pioneered several agile design and verification techniques that have been successfully integrated into the project. His work has been recognized with the CAS President’s Special Award, the ICT Director’s Special Award (Xia Peisu Award), and the National Scholarship. His research contributions have been published in leading venues such as MICRO, DAC, and JCST. Notably, XiangShan and its agile design methodology were selected as one of 2022 IEEE Micro Top Picks, recognizing it as one of the year’s most influential conference papers to computer architecture.
Research area：
Agile chip development, open-source processor design, and high-performance microarchitecture.
Selected papers：
(1) Kunlin You, Yinan Xu, Kehan Feng, Luoshan Cai, Yaoyang Zhou, Yungang Bao. DiffTest-H: Toward Semantic-Aware Communication in Hardware-Accelerated Processor Verification. 58th IEEE/ACM International Symposium on Microarchitecture (MICRO’25).
(2) Yinan Xu, Sa Wang, Dan Tang, Ninghui Sun, and Yungang Bao. PathFuzz: Broadening Fuzzing Horizons with Footprint Memory for CPUs. 61st ACM/IEEE Design Automation Conference (DAC’24).
(3) Yi-Nan Xu, Zi-Hao Yu, Kai-Fan Wang, Hua-Qiang Wang, Jia-Wei Lin, Yue Jin, Lin-Juan Zhang, Zi-Fei Zhang, Dan Tang, Sa Wang, Kan Shi, Ning-Hui Sun, Yun-Gang Bao. Functional Verification for Agile Processor Development: A Case for Workflow Integration. Journal of Computer Science and Technology 38(4): 737−753 July 2023.
(4) Yinan Xu, Zihao Yu, Dan Tang, Guokai Chen, Lu Chen, Lingrui Gou, Yue Jin, Qianruo Li, Xin Li, Zuojun Li, Jiawei Lin, Tong Liu, Zhigang Liu, Jiazhan Tan, Huaqiang Wang, Huizhe Wang, Kaifan Wang, Chuanqi Zhang, Fawang Zhang, Linjuan Zhang, Zifei Zhang, Yangyang Zhao, Yaoyang Zhou, Yike Zhou, Jiangrui Zou, Ye Cai, Dandan Huan, Zusong Li, Jiye Zhao, Zihao Chen, Wei He, Qiyuan Quan, Xingwu Liu, Sa Wang, Kan Shi, Ninghui Sun, Yungang Bao. Towards Developing High Performance RISC-V Processors Using Agile Methodology. 55th IEEE/ACM International Symposium on Microarchitecture (MICRO’22).
