Biography：
Graduated with a Ph.D. from the Institute of Software,Chinese Academy of Sciences,in June 2024. Since July 2024,has been employed at the Institute of Computing Technology,Chinese Academy of Sciences,working on agile chip design methodologies and formal verification.
Research area：
Formal methods,hardware-software verification,and deep hardware-software integration.
Selected papers：
[1]Yufeng Li,Yiwei Ci,Qiusong Yang,Enyuan Tian. Efficient processor verification by tautologies-derived universal properties model checking. Integration 2025: 102502
[2]Yufeng Li,Qiusong Yang,Yiwei Ci,Enyuan Tian. SEPE-SQED: Symbolic Quick Error Detection by Semantically Equivalent Program Execution. DAC 2024: 258:1-258:6
[3]Yufeng Li,Yiwei Ci,Qiusong Yang. TIUP: Effective Processor Verification with Tautology-Induced Universal Properties. ASP-DAC 2024: 269-274
