Associate Researcher/Senior Engineer
  • Dejun Jiang

  • E-mail: jiangdejun@ict.ac.cn

Biography:

Jiang Dejun received Ph.D. degree of Compute Science at Vrije Universiteit Amsterdam, Netherlands in 2012. At the same year, he became an assistant professor at Institute of Computing Technology, Chinese Academy of Sciences (CAS). From 2015 to now, he is an Associate Professor at Institute of Computing Technology CAS. Starting from 2016, he served as a teacher in the University of Chinese Academy of Sciences. He served as the professional committee member of CCF Information Storage Committee and CCF High Performance Computing Committee. He is also a member of Youth Innovation Promotion Association CAS. His research interests include storage architecture and system, operating system, and distributed system. In recent years, he has published over 20 papers at top conferences, including ATC, MSST, PACT, TACO, ICS, ICCD, WWW, JCST. 

Research area:

Storage System and Architecture, Operating System, Distributed System

Selected papers:

[1]Liuying Ma, Zhenqing Liu, Jin Xiong and Dejun Jiang, QWin: Core Allocation for Enforcing Differentiated Tail Latency SLOs at Shared Storage Backend, 42nd IEEE International Conference on Distributed Computing Systems (ICDCS 2022)

[2]Ying Wang, Dejun Jiang, Jin Xiong, NUMA-Aware Thread Migration for High Performance NVMM File Systems, In Proceedings of the 36th International Conference on Massive Storage Systems and Technology (MSST 2020)

[3]Ying Wang, Dejun Jiang, Jin Xiong, Revisiting Virtual File System for Metadata Optimized Non-Volatile Main Memory File System, In Proceedings of the 36th International Conference on Massive Storage Systems and Technology (MSST 2020)

[4]Shukai Han, Dejun Jiang, Jin Xiong, LightKV: A Cross Media Key Value Store with Persistent Memory to Cut Long Tail Latency, In Proceedings of the 36th International Conference on Massive Storage Systems and Technology (MSST 2020)

[5]Wei, Wei, Jiang, Dejun, Xiong, Jin, Chen, Mingyu HAP: Hybrid-Memory-Aware Partition in Shared Last-Level Cache. ACM Transactions on Architecture and Code Optimization, Vol. 14, No. 3, Article 24. 2017

[6]Fei Xia, Dejun Jiang, Jin Xiong, Ninghui Sun. HiKV: A Hybrid Index Key-Value Store for DRAM-NVM Memory Systems. In Proceedings of 2017 USENIX Annual Technical Conference. 2017