Keynote 2: Cloud 3.0: Optimizing for the Extremes

Speaker: Christos Kozyrakis

Abstract:The elasticity and usage-based pricing of cloud services has made them the preferred computing platform for a wide range of workloads. However, emerging applications are now placing extreme requirements on the cloud infrastructure: micro-services require microsecond-scale latencies across large datacenters; real-time analytics on massive datasets require the ability to scale computations from zero to thousands of nodes and back within seconds; and many machine-learning algorithms require petaops of sustained performance. Can we design cloud infrastructure that meets such extreme requirements while maintaining the cost effectiveness expected from utility computing? In this talk, we will revisit the software and hardware stack for cloud computing and discuss key opportunities towards this goal. Specifically, we will discuss distributed frameworks for massively scalable workloads, cluster management in the presence of thousands of system and application level knobs, and  programming and hardware technology needed for practical specialized computing.

Bio: Christos Kozyrakis is a Professor of of Computer Science and Electrical Engineering at Stanford University (USA). He works on architecture, system software, and programming models for systems ranging from cellphones to warehouse-scale datacenters. His past research includes energy-efficient data-parallel architectures, transactional memory technology, and hardware support for robust security abstractions.  His research currently focuses on hardware and software techniques for resource efficient cloud computing. Christos holds a PhD degree from the University of California at Berkeley (USA) and a BS degree from the University of Crete (Greece). He is an ACM Fellow, an IEEE Fellow, and the recipient of distinctions such as the ACM SIGARCH Maurice Wilkes award and the NSF Career award.

Keynote 3: Networking Technologies and Middleware for Next-Generation Data Centers: Opportunities and Challenges

Speaker: Dhabaleswar K. (DK) Panda

Abstract:This talk will focus on emerging technologies and middleware for designing next-generation data centers with high-performance and scalability. The role and significance of RDMA technology with InfiniBand and RoCE (v1 and v2) will be presented. Challenges in designing high-performance middleware for running Big Data and Deep Learning applications on datacenters will be focused. An overview of RDMA-based designs for Spark, Hadoop, HBase, and Memcached will be presented. On the Deep Learning side, RDMA-based designs for popular Deep Learning frameworks such as TensorFlow, Caffe, and CNTK will be focused. The talk will conclude with challenges in providing efficient virtualization support for next generation datacenters with CPUs and accelerators.

Bio: DK Panda is a Professor and University Distinguished Scholar of Computer Science and Engineering at the Ohio State University. He has published over 400 papers in the area of high-end computing and networking. The MVAPICH2 (High Performance MPI and PGAS over InfiniBand, Omni-Path, iWARP and RoCE) libraries, designed and developed by his research group (http://mvapich.cse.ohio-state.edu) are currently being used by more than 2,800 organizations worldwide (in 85 countries). More than 426,000 downloads of this software have taken place from the project’s site. This software is empowering several InfiniBand clusters (including the 1st, 15th, 20th, and 44th ranked ones) in the TOP500 list. The RDMA packages for Apache Spark, Apache Hadoop and Memcached together with OSU HiBD benchmarks from his group (http://hibd.cse.ohio-state.edu) are also publicly available. These libraries are currently being used by more than 245 organizations in 31 countries. More than 23,300 downloads of these libraries have taken place. A high-performance and scalable version of the Caffe framework is available from his group (http://hidl.cse.ohio-state.edu). Prof. Panda is an IEEE Fellow. More details about Prof. Panda are available at http://www.cse.ohio-state.edu/~panda.

Keynote 4: Inside Alibaba Cloud: Lessons, Challenges and Opportunities of Cloud Storage at Hyperscale

Speaker: Jiesheng Wu

Abstract:In this talk, we present the architecture of Pangu system — Alibaba storage infrastructure managing datacenter as a storage appliance，providing strong consistency with high availability and performance, and supporting Cloud Storage services.  We share some of design choices and lessons learnt from years of research and development and from experience serving millions of customers. This talk also describes challenges faced as the cloud computing advances to the next wave, as well as opportunities created, by Alibaba Cloud Storage.

Bio: Jason Wu is a senior director of engineering at Alibaba leading the development of Alibaba storage infrastructure and Cloud Storage services. In 2014, he joined Alibaba Cloud Seattle office. Before coming to Alibaba, Jason joined Microsoft Azure storage team in 2008 and was a principal development manager leading the development of Azure storage. In 2004, he joined Ask.com and worked as a senior manager on the search infrastructure and the Crawler system. From 1996 to 1999, he worked as a research engineer on the development of Dawning-series supercomputer systems at National Center for Intelligent Computing system (NCIC), Institute of Computing Technology (ICT).

Keynote 5: Communication at the Speed of Memory

Speaker: Paolo Faraboschi

Abstract:Our IT infrastructure is becoming unbalanced to access and mine the unprecedented amount of data that it’s drowning it. While it is relatively easy to provision compute resources, data resources are much more challenging. This is true across memory, storage, and the system interconnects necessary to access them, which are all going through profound transformations. New applications and irregular data patterns are causing us to rethink the traditional shared-nothing, partitionable approach to data.Disruptive technologies, such as storage-class memory and silicon photonics, are creating discontinuities in the traditional memory/storage hierarchy. This talk discusses why we need a new approach to architect data movement, and what role the recently announced Gen-Z protocol can play (www.genzconsortium.org). Gen-Z is and open systems interconnect designed to provide memory semantic access to data and devices via direct-attached, switched, or fabric topologies. It is designed to address fabric needs within individual servers, at rack-scale, and all the way to next-generation exascale HPC systems. Gen-Z scalability comes from a combination of protocol features and optimized implementations. The talk covers the key aspects of Gen-Z as a high-performance interconnect, such as CPU-initiated atomics, high efficiency RDMA via memory semantics, and fast acting congestion control, and how these features provide the basis to enable next-generation exascale systems. The talk also covers some of The Machine research work at Hewlett-Packard Labs to push the boundaries of a “memory semantics” fabric and truly revolutionize the memory and storage hierarchy towards Memory-Driven Computing.

Bio: Paolo Faraboschi is a Fellow and VP at Hewlett Packard Enterprise Labs. His interests are at the intersection of systems, architecture, and software. He is currently researching memory-driven computing technologies and their use for exascale computing. He was the lead hardware architect of The Machine project, researching how we can build better memory-driven computing systems for big data problems. From 2010 to 2014, he worked on low-energy servers and HP project Moonshot. From 2004 to 2009, at HP Labs in Barcelona, he led a research activity on scalable system-level simulation and modelling. From 1995 to 2003, at HP Labs Cambridge, he was the principal architect of the Lx/ST200 family of VLIW cores, widely used in video SoCs and HP’s printers. Paolo is an IEEE Fellow and an active member of the computer architecture community. He is an author on 30 patents, over 100 publications, and the book “Embedded Computing: a VLIW approach”. Before joining HP in 1994, he received a Ph.D. in EECS from the University of Genoa, Italy.

Keynote 6: ScaleSimulator-a fast and cycle-accurate parallel simulator for DC architectural exploration

Speaker: Xiongli Gu

Abstract:ScaleSimulator is a new parallel simulation platform developed in Huawei that can run fast and support full system simulation for datacenter chips. It has the following three main characteristics: Fast – Take advantage of parallel hardware in order to expedite simulation execution time Full system – system level that can execute real-life unmodified OS and software stack Flexible – simulate different level architectures, from single-core to multi-core, I/O, DCN and etc. Thus it can efficiently support the architecture exploration for chip design in datacenter.

Bio: Xiongli Gu is a senior engineer of Datacenter technology research lab, Huawei, Ltd.He received his Master & PhD degrees in Information science & Electronic Engineering from Zhejiang university, 2008 and 2011, respectively, and his main research area was computing architecture. After graduated from university, he joined Huawei and worked in the projects of mission critical server interconnection chip design, many-core sever chip design and modeling&simulation.Now he is the associate director of modeling & simulation team for chips of datacenter.

Keynote 7: Intel’s practices on platform challenges for deep learning aided medical image diagnosis

Speaker: Weifeng Yao

Abstract:This speech describes Intel’s practices on deep learning aided medical image diagnosis. Medical images diagnosis is different from the popular well-studied problems like IMAGENET and COCO, both from data characteristics and from problem caring points, which presents new challenges both to algorithm and computation platforms. We will introduce some of Intel°Øs researches/practices and results on these new challenges.

Bio: Weifeng Yao works on AI solutions enabling and optimization at Intel’s Data Center Group as deep learning technical lead and senior expert. He received his MSc from Southeast University in Signal Processing. His work focuses on various top-to-down deep learning based solutions research, enabling and optimizations on Intel platforms. Before Intel, he was an algorithm lead in Cheetah on personalized recommendation system and an algorithm lead at Baidu on machine learning based localization. He holds 4 China patents and 1 US patent.