Biography：
Xu Zhang, Assistant Professor at the Institute of Computing Technology, Chinese Academy of Sciences. He received his bachelor's degree from the University of Chinese Academy of Sciences (UCAS) in 2019, and completed his Ph.D. at the Institute of Computing Technology, Chinese Academy of Sciences in 2025. During his doctoral studies, he was honored as an Outstanding Graduate of Beijing.
Research area：
His researches mainly focus on Memory Semantic Interconnections (e.g. OpenCAPI and CXL), Distributed Shared Memory System, Intra-Rack network, and RDMA. At present, He is actively involved in the performance optimization and development of open-source memory controller YuQuan.
Selected papers：
X. Zhang, K. Liu, H. Yuan, X. Zheng, Y. Chang, Y. Shan, G. Zhang, K. Zhang, Y. Bao, M. Chen, and C. Wang. “DRack: A CXL-Disaggregated Rack Architecture to Boost Inter-Rack Communication,” 2025 USENIX Annual Technical Conference (USENIX ATC ‘25), Boston, MA, USA.
Luming Wang, Xu Zhang, Songyue Wang, Zhuolun Jiang, Tianyue Lu, Mingyu Chen, Siwei Luo, and Keji Huang. 2024. Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access. ACM Trans. Archit. Code Optim. 21, 3, Article 55 (September 2024), 28 pages.
X. Zhang, T. Lu, Y. Chang, K. Zhang and M. Chen, “Morpheus: An Adaptive DRAM Cache with Online Granularity Adjustment for Disaggregated Memory,” 2023 IEEE 41st International Conference on Computer Design (ICCD), Washington, DC, USA, 2023, pp. 134-141.
X. Zhang, Y. Chang, T. Lu, K. Zhang, and M. Chen, “Rethinking Design Paradigm of Graph Processing System with a CXL-like Memory Semantic Fabric,” 2023 IEEE/ACM 23rd International Symposium on Cluster, Cloud and Internet Computing (CCGrid), Bangalore, India, 2023, pp. 25-35.
