Biography：
Xuying Zhao，obtained a Doctor of Engineering degree from the Institute of Automation, Chinese Academy of Sciences in January 2018. In April 2018, joined the Institute of Computing Technology, Chinese Academy of Sciences. In 2022, promoted to the rank of senior engineer. She has participated in the research and development of the baseband chip for mathematical processors in the Strategic Priority Research Program of the Chinese Academy of Sciences, the research and development of industrial-grade 5G terminal baseband chips in a Ministry of Science and Technology research project. She was also in charge of the industrialization of the baseband chip for Tiantong satellite communication. The self-developed chips have been successfully applied to flagship mobile phones of the Chinese terminal manufacturers such as Honor and Xiaomi.
Research area：
Application-Specific Integrated Circuit (ASIC) design，Communication baseband chip design，Hardware formal verification
Selected papers：
[1] Zhao Xuying, Li Huan, Wang Xiaoqin, et al. Research on a New 2D Configurable Coprocessor Architecture for Communication Applications[J]. Journal of Harbin Engineering University, 2018, 39(12): 143-148.
[2] Zhao Xuying, Li Huan, Wang Xiaoqin, et al. High-Performance Configurable Viterbi Decoder Based on Sliding Window Pipelining[J]. Microelectronics & Computer, 2018, 35(2): 32-36.
[3] Zhao X , Li H , Wang X . A high performance multi-standard Viterbi decoder[C]// 2017 7th IEEE International Conference on Electronics Information and Emergency Communication (ICEIEC). IEEE, 2017.
