Associate Researcher/Senior Engineer
  • Kan Shi

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Kan Shi received his Ph.D. degree from Imperial College London in 2015. He has been an associate professor in ICT since 2021. From 2015 to 2021, he was a senior engineer of chip design at Intel's UK R&D Center and a research scientist at Intel Research Institute. He has won the HiPEAC Paper Award twice and a best paper nomination (FPT). He serves as a TPC member of many top international conferences in the field of FPGA. He has an independently published Chinese book "Detailed Explanation of FPGA: Driving Engine in the Age of Artificial Intelligence".

Research area:

His research direction contains programmable logic chip FPGA, cloud computing and data center architecture, agile chip design and verification.

Selected papers:

1.Kan Shi, David Boland and George A. Constantinides, Imprecise Datapath Design: An Overclocking Approach, ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2014. (Invited Paper)

2.Kan Shi, David Boland, George A. Constantinides, Efficient FPGA Implementation of Digit Parallel Online Arithmetic Operators, Proc. International Conference of Field Programmable Technology (FPT), Shanghai, 2014. (Best Paper Candidate)

3.Kan Shi, David Boland, Ed Stott, Samuel Bayliss and George A. Constantinides, Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs, Proc. ACM/IEEE Design Automation Conference (DAC), San Francisco, 2014. (HiPEAC Paper Award)

4.Kan Shi, David Boland, George A. Constantinides, Accuracy-Performance Trade-offs on an FPGA Through Overclocking, Proc. IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Seattle, 2013. (HiPEAC Paper Award)