• Abstract: This talk presents, Project PHI (Pervasive Hierarchical Intelligence) a holistic effort to provide a comprehensive solution for making immersive machine intelligence a reality.  Our guiding principle is to retain as much generality and automation while delivering large performance and efficiency gains through specialization and acceleration for a wide range of learning and intelligence workloads. As the first milestones of Project PHI, we have developed Tabla and DnnWeaver, which are open source and publically available (http://act-lab.org/artifacts/tabla/ and http://act-lab.org/artifacts/dnnweaver/). DnnWeaver is the very first open-source hardware acceleration framework for deep neural networks. Tabla is a cross-stack solution—spanning from programming language to the hardware—that rethinks the hardware/software abstraction by delving into the theory of machine learning. It leverages the insight that many learning algorithms can be solved using stochastic gradient descent that minimizes an objective function. The solver is fixed while the objective function changes with the learning algorithm. Therefore, Tabla uses stochastic optimization as the abstraction between hardware and software. Consequently, programmers specify the learning algorithm by merely expressing the gradient of the objective function in our domain specific language. Tabla then automatically generates the synthesizable implementation of the accelerator for scale-out FPGA realization using a set of template designs. Real hardware measurements show orders of magnitude higher performance and power efficiency while the programmer only writes 60 lines of code. Next, the talk ventures to the edge domain and shows how utilizing algorithmic insights enables us to match the server-grade GPU performance for DNN acceleration within milli-Watt regime. These encouraging results show that rethinking the hardware/software abstractions from an algorithmic perspective can open new dimensions in system design for Pervasive Hierarchical Intelligence.

• Bio: Hadi was awarded early tenure at the University of California, San Diego (UCSD), where he is an associate professor in Computer Science and Engineering. Prior to UCSD, he was an assistant professor in the School of Computer Science at the Georgia Institute of Technology from 2013 to 2017. There, he was the inaugural holder of the Catherine M. and James E. Allchin Early Career Professorship. Hadi is the founding director of the Alternative Computing Technologies (ACT) Lab, where his team is developing new technologies and cross-stack solutions to build the next generation computer systems. He is the Associate Director of Industry Research in the Center on Machine Integrated Computing and Security (MICS). Dr. Esmaeilzadeh received his Ph.D. from the Department of Computer Science and Engineering at the University of Washington in 2013. His Ph.D. dissertation received the 2013 William Chan Memorial Dissertation Award from the University of Washington. Hadi has received the Air Force Office of Scientific Research Young Investigator Award (2017), College of Computing Outstanding Junior Faculty Research Award (2017), Qualcomm Research Award (2017 and 2016), Google Research Faculty Award (2016 and 2014), Microsoft Research Award (2016 and 2017), and Lockheed Inspirational Young Faculty Award (2016). His team was awarded the Qualcomm Innovation Fellowship in 2014, one of his students is a Microsoft Research Fellow, and another won the 2017 National Center for Women & IT (NCWIT) Collegiate Award. Four of his undergraduate students have been awarded the Georgia Tech President’s Undergraduate Research Award (PURA). His research has been recognized by four Communications of the ACM Research Highlights, four IEEE Micro Top Picks, recently one more nomination for Communications of the ACM Research Highlights, one more honorable mention in IEEE Micro Top Picks, and a Distinguished Paper Award in HPCA 2016.  Hadi’s work on dark silicon has also been profiled in New York Times. More information is available on his webpage,http://cseweb.ucsd.edu/~hadi/ .

Break

• Abstract: A new generation of computing devices is emerging. A key feature of these devices will be their ability to understand the world around them and provide real time responses in complex situations, emulating human perception and problem solving. To perform these tasks, they will require a huge computational power, which is specially challenging to attain in devices with very tight constraints in energy consumption. This dramatic improvements in energy-efficiency will be even more challenging due to the slowdown in process technology scaling. Given the limited contribution from technology, most improvements will have to come from architecture. General purpose architectures have reached a point of diminishing returns after five decades of evolution. On the other hand, domain-specific architectures offer great potential to fulfill the requirements of these emerging devices and they will be key to provide innovative solutions in computing systems in the forthcoming future. In this talk, we will describe this trend and will illustrate it with a particular case study focused on speech recognition.

• Bio: Antonio González received his Ph.D. degree from the Universitat Politècnica de Catalunya (UPC), in Barcelona, Spain, in 1989. He joined the faculty of the Computer Architecture Department of UPC in 1986 and became a Full Professor in 2002. He was the founding director of the Intel Barcelona Research Center from 2002 to 2014. 
                    His research has focused on computer architecture. In this area, Antonio holds 46 patents, has published over 350 research papers and has given over 100 invited talks. He has also made multiple contributions to the design of the architecture of several Intel processors. 
                    Antonio has been program chair for ICS 2003, ISPASS 2003, MICRO 2004, HPCA 2008 and ISCA 2011, and general chair for MICRO 2008 and HPCA 2016 among other symposia. He has served on the program committees for over 100 international symposia in the field of computer architecture, and has been Associate Editor of the IEEE Transactions on Computers, IEEE Transactions on Parallel and Distributed Systems, IEEE Computer Architecture Letters, ACM Transactions on Architecture and Code Optimization, ACM Transactions on Parallel Computing, and Journal of Embedded Computing. 
                    Antonio’s awards include the award to the best student in computer engineering in Spain graduating in 1986, the 2001 Rosina Ribalta award as the advisor of the best PhD project in Information Technology and Communications, the 2008 Duran Farrell award for research in technology, the 2009 Aritmel National Award of Informatics to the Computer Engineer of the Year, the 2013 King James I award for his contributions in research on new technologies, and the 2014 ICREA Academia Award. He is an IEEE Fellow.

 

Thomas F. Wenisch, University of Michigan

lunch

• Abstract:  Cutting-edge deep neural networks are trending towards more compute and   greater complexity to achieve better accuracy, often requiring billions   of operations to evaluate a single input. However, this makes them   difficult to serve in real-time   in the cloud, where we are constrained by latency, power, cost and   plateauing of Moore’s Law. Demand for evaluating these models at   millisecond scale latencies has led to an explosion of Neural Processor   Units (NPUs) specialized for DNN computation. While   hardened NPUs can be made fast and power efficient, they lack the   flexibility and extensibility to support rapidly evolving DNN models. In   this talk, we present Project Brainwave, a vertically integrated   platform for real-time AI that is currently in production   at Microsoft. By leveraging the flexibility of FPGAs and a scale-out   deployment architecture, the Brainwave platform can evaluate a variety   of large modern deep DNNs at sub-millisecond latencies with no batching.   The talk will dive into the details of the   Brainwave stack and discuss the fundamental techniques we used to   enable low latency inference.

• Bio:  Ming Liu is a Senior Research Hardware Engineer at Microsoft where he is   a core member of Project Brainwave and Project Catapult aimed at   accelerating AI using hyperscale FPGAs in the cloud. His research   interests are in hardware design,   application specific accelerators, computer architecture and machine   learning. Ming holds a MS from MIT and a BASc from the University of   Toronto.

   

• Abstract: Cloud applications have recently undergone a major redesign, switching from monolithic implementations that package the entire functionality of the application in a single binary, to large numbers of loosely-coupled microservices. This shift comes with several advantages, such as facilitating and accelerating development and deployment, however, it also introduces several challenges. First, microservices change several assumptions current datacenter servers are designed with. Second, the dependencies between microservices make scheduling and resource management challenging, as any poorly-managed microservice can introduce end-to-end QoS violations. In this talk I will first discuss the implications microservices have on datacenter server design and cluster management, and then describe two ways in which data-driven approaches can help manage resources in a way that guarantees end-to-end QoS, and diagnose performance, efficiency, and security issues in a practical and scalable manner.

• Bio: Christina Delimitrou is an Assistant Professor and the John and Norma Balen Sesquicentennial Faculty Fellow at Cornell University, where she works on computer architecture and computer systems. Specifically, Christina focuses on improving the resource efficiency of large-scale cloud infrastructures by revisiting the way these systems are designed and managed. She is the recipient of a Facebook Faculty Research Award, 3 IEEE Micro Top Picks awards, a Facebook Graduate Fellowship, and a Stanford Graduate Fellowship. Before joining Cornell, Christina received her PhD from Stanford University. She had previously received an MS also from Stanford, and a diploma in Electrical and Computer Engineering from the National Technical University of Athens. More information can be found at:http://sail.ece.cornell.edu