Yungang Bao (包云岗)
       Professor                                                                                         中文版简历 (Chinese version)

Yungang is a professor of the State Key Laboratory of Computer Architecture, Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS). He is the associate director of Research Center for Advanced Computer System (ACS) and is leading the Frontier System Lab (FSL) that focuses on datacenter architecture. Yungang received his BS degree in computer science from Nanjing University in 2003, and his PhD degrees in computer engineering from ICT, CAS in 2008, supervised by Prof. Jianping Fan and Prof. Mingyu Chen. During his PhD study, he led the Hybrid Hardware/Software Memory Trace Tool (HMTT) project. During 2010-2012, he did postdoc research in Department of Computer Science, Princeton University, working with Prof. Kai Li on the Princeton Application Repository for Shared-Memory Computers (PARSEC) project. He was the winner of CCF-Intel Young Faculty Researcher Program of the year for 2013.


    NO. 6, Ke Xue Yuan South Road, Zhongguancun,
    Beijing, P.R.China 100190 Phone: (86)10-62601019
    Email:  baoyg at ict dot ac dot cn

  • Computer Architecture

  • Operating System

  • System Performance Modeling and Evaluation

  • CV

  • PARD: Programmable Architecture for Resourcing-on-Demand
    This project investigates architectural support for resource-efficient datacenters based on the insight: The Computer as a Network (CaaN). The goal is to reconstruct a computer to be an SDN-like (software-defined networking) network that enables new functionalities such as hardware virtualization w/o hypervisor, architectural supported quality-of-service (QoS) and differentiaed services. PARD is able to improve datacenter's resource utilization while ensuring applications' QoS.
    [News] June. 2016: The open-sourced FPGA-based PARD prototype released at ISCA 2016: CaaN Tutorial
    [News] Oct. 2015: Invited to parcipate in Dastughl Seminar on "Rack-Scale Computing": Dastuhl Seminar
    [News] Mar. 2015: Presentation at ASPLOS'15: Slides (12MB)
    [News] Jan. 2015: GEM5-based full-system PARD simulator is open sourced: Github
    [News] Nov. 2014: Our first paper describing the PARD idea is accepted by ASPLOS'15.

  • PARSEC 3.0: The Princeton Application Repository for Shared-Memory Computers
    PARSEC 3.0 has made three major changes: 1) Add network benchmarks as well as a user-level parallel TCP/IP stack. 2) Provide SPLASH-2 and the inputs-enlarged SPLASH-2x. 3) Redesign the framework for supporting external suites.
    [News] Feb. 2015: New version updated.
    [News] Sept. 2012: Beta version released.

  • HMTT: A Hybrid Hardware/Software Memory Trace Tool
    We provide off-chip memory traces of many real-world applications, e.g., SPECCPU, SPECjbb, TPC-H/TPC-C on Oracle, and SPECWeb on Apache, with abundant important information, such as timestamp, pid, cpu-request/io-request, r/w, virt_addr and phys_addr. However, the trace sizes are quite large, being several hundred Gigabytes. We would like to provide the traces to the research community via sending hard disks. If you need the traces, please contact us.
    [News] Feb. 2013: HMTT Tutorial @ HPCA 2013 [slides].

Selected Publications:
(Full List)
  • Jiuyue Ma, Xiufeng Sui, Ninghui Sun, Yupeng Li, Zhihao Yu, Bowen Huang, Tiani Xu, Zhicheng Yao, Yun Chen, Haibin Wang, Lixing Zhang, Yungang Bao, Supporting Differentiated Services in Computers via Programmable Architecture for Resourcing-on-Demand (PARD) , in the 20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2015. [pdf] [slides]

  • Zehan Cui, Sally A. McKee, Zhongbin Zha, Yungang Bao, Mingyu Chen, DTail: A Flexible Approach to DRAM Refresh Management , to appear in ACM International Conference on Supercomputing (ICS), 2014. [pdf]

  • Lei Liu, Yong Li, Zehan Cui, Yungang Bao, Mingyu Chen, Chengyong Wu, Going Vertical in Memory Management: Handling Multiplicity by Multi-policy , to appear in the 41st International Symposium on Computer Architecture (ISCA), 2014. [pdf]

  • Rui Ren, Jiuyue Ma, Xiufeng Sui, and Yungang Bao, D^2P: A Distributed Deadline Propagation Approach to Tolerate Long-Tail Latency in Datacenters , appear in 5th ACM Asia-Pacific Workshop on Systems (APSys), 2014. [pdf]

  • Tianshi Chen, Qi Guo, Olivier Temam, Yue Wu, Yungang Bao, Zhiwei Xu, and Yunji Chen, Statistical Performance Comparisons of Computers, to appear in IEEE Transactions on Computers (IEEE TC), 2014. [pdf]

  • Zehan Cui, Licheng Chen, Yungang Bao, Mingyu Chen, A Swap-based Cache Set Index Scheme to Leverage both Superpage and Page Coloring Optimizations , to appear in the Design Automation Conference (DAC), 2014. [pdf]

  • Licheng Chen, Zhipeng Wei, Zehan Cui, Mingyu Chen, Haiyang Pan, Yungang Bao, CMD: Classification-based Memory Deduplication through Page Access Characteristics , in the 10th ACM SIGOPS/SIGPLAN International Conference on Virtual Execution Environments (VEE), 2014. [pdf]

  • Lei Liu, Zehan Cui, Yong Li, Yungang Bao, Mingyu Chen, Chengyong Wu, BPM/BPM+: Software-based Memory Partitioning Mechanisms for Eliminating DRAM Bank-/Channel-level Interferences in Multicore Systems , to appear in the ACM Transactions on Architecture and Code Optimization (TACO), 2014. [pdf]

  • Yongbing Huang, Licheng Chen, Zehan Cui, Yuan Ruan, Yungang Bao, Mingyu Chen, Ninghui Sun, HMTT: A Hybrid Hardware/Software Tracing System for Bridging the DRAM Access Trace's Semantic Gap , to appear in the ACM Transactions on Architecture and Code Optimization (TACO), 2014. [pdf]

  • Licheng Chen, Yanan Wang, Zehan Cui, Yongbing Huang, Yungang Bao, Mingyu Chen, Scattered Superpage: A Case for Bridging the Gap between Superpage and Page Coloring, Proceedings of the 31st IEEE International Conference on Computer Design (ICCD), Asheville, NC, 2013. [pdf]

  • Lei Liu, Zehan Cui, Mingjie Xing, Yungang Bao, Mingyu Chen, Chengyong Wu, A Software Memory Partition Approach for Eliminating Bank-level Interference in Multicore Systems, International Conference on Parallel Architectures and Compilation Techniques (PACT), 2012. [pdf]

  • Yongbing Huang, Zehan Cui, Licheng Chen, Wenli Zhang, Yungang Bao, Mingyu Chen, HaLock: Hardware-Assisted Lock Contention Detection in Multithreaded Applications, International Conference on Parallel Architectures and Compilation Techniques (PACT), 2012. [pdf]

  • Pengfei Zhu, Mingyu Chen, Yungang Bao, Licheng Chen, and Yongbing Huang, Trace-driven Simulation of the Memory System Scheduling in Multithread application, ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (MSPC) co-located with PLDI, 2012. [pdf]

  • Licheng Chen, Zehan Cui, Yongbing Huang, Yungang Bao, Guangming Tan, Mingyu Chen, A Lightweight Hybrid Hardware/Software Approach for Object-Relative Memory Profiling, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), New Brunswick, NJ, April 1-3, 2012. [pdf], [ppt]

  • Erlin Yao, Yungang Bao, Mingyu Chen, What Hill-Marty model learn from and break through Amdahl's law?, Information Processing Letters (IPL), 2011.[pdf]

  • Guangming Tan, Linchuan Li, Sean Triechle, Everett Phillips, Yungang Bao, Ninghui Sun, Fast Implementation of DGEMM on Fermi GPU, ACM/IEEE Supercomputing (SC), 2011. [pdf]

  • Zehan Cui, Yan Zhu, Yungang Bao and Mingyu Chen, A Fine-grained component-level power measurement method, The First International Workshop on Power Measurement and Profiling (PMP) in conjunction with IEEE IGCC, 2011. [pdf]

  • Dan Tang, Yungang Bao, Weiwu Hu, Mingyu Chen, DMA Cache: Using On-Chip Storage to Architecturally Separate I/O Data from CPU Data for Improving I/O Performance, the 16th IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2010. [pdf],[ppt]

  • Erlin Yao, Yungang Bao, Guangming Tan, Mingyu Chen, Extending Amdahl's Law in the Multicore Era, ACM SIGMETRICS Performance Evaluation Review (PER), Volume 37 , Issue 2, September 2009. [pdf]

  • Dan Tang, Yungang Bao, Yunji Chen, Weiwu Hu, Mingyu Chen, Exploiting the Produce-Consume Relationship in DMA to Improve I/O Performanc, Workshop on The Influence of I/O on Microprocessor Architecture (IOM) in conjunction with the 15th International Symposium on High-Performance Computer Architecture (HPCA), Raleigh, North Carolina, February 15, 2009. [pdf],[ppt],

  • Yungang Bao, Mingyu Chen, Yuan Ruan, Li Liu, Jianping Fan, Qingbo Yuan, Bo Song, Jianwei Xu, HMTT: A Platform Independent Full-System Memory Trace Monitoring System, International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS),Annapolis, Maryland, USA, June 2-6,2008.[pdf]

Professional Activities:
  • PC Member, SC 2016.
  • PC Member, APSys 2016.
  • PC Member, ICS 2016.
  • PC Member, ASPLOS 2016.
  • PC Member, ICS 2015.
  • PC Member, IISWC 2014.
  • General co-chair, APSys 2014.
  • Program co-chair, ASBD 2014, ASBD 2015.
  • General co-chair, ChinaSys 2013 Spring.
  • HPCA 2013, External Reviewer
  • The 2nd International Workshop on Power Measurement and Profiling (PMP) 2012, Program Co-chair
  • IEEE Transactions on Computers(TC), Reviewer
  • IEEE Transactions on VLSI Systems (TVLSI), Reviewer
  • IEEE Transactions on Parallel and Distributed Systems (TPDS), Reviewer
  • Journal of Parallel and Distributed Computing (JPDC), Reviewer
  • The 1st International Workshop on Power Measurement and Profiling (PMP), 2011, Program Committee
  • IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA), 2011, Program Committee
  • International Conference on High Performance Computing (HiPC), 2011, External Reviewer
  • International Conference on Supercomputing (ICS) 2010, External Reviewer
  • Supercomputing (SC) 2009, External Reviewer
  • Supercomputing (SC) 2008, External Reviewer
  • HPC-Asia'05 External Reviewer

Colleagues and Collaborators:

Last updated: July 8, 2016.