|08:45 - 08:50||Welcome Remarks|
|08:50 - 09:40||Keynote talk : EXTREME-SCALE COMPUTER ARCHITECTURE: ENERGY EFFICIENCY FROM THE GROUND UP [pdf]|
|Josep Torrellas, University of Illinois Urbana-Champaign|
Abstract: As we move to integration levels of 1,000-core processor chips, it is clear that
energy and power consumption are the most formidable obstacles. To construct
such a chip, we need to rethink the whole compute stack from the ground up for
energy efficiency and attain Extreme-Scale Computing. First of all, we want
to operate at low voltage, since this is the point of maximum energy efficiency.
Unfortunately, in such an environment, we have to tackle substantial process
variation. Hence, it is important to design efficient voltage regulation, so
that each region of the chip can operate at the most efficient voltage and
frequency point. At the architecture level, we require simple cores organized
in a hierarchy of clusters. Moreover, we also need techniques to reduce the
leakage of on-chip memories and to lower the voltage guardbands of logic.
Finally, data movement should be minimized, through both hardware and software
techniques. With a systematic approach that cuts across multiple layers of
the computing stack, we can deliver the required energy efficiencies.
Bio: Josep Torrellas is a Professor of Computer Science and Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign.
He is a Fellow of IEEE and ACM. He is the Director of the Center for Programmable Extreme-Scale Computing, a center focused on architectures for extreme energy and power efficiency. He was until recently the
Director of the Intel-Illinois Parallelism Center (I2PC), a center created by Intel to advance parallel computing in clients. He has made contributions to parallel computer architecture in the areas of shared memory multiprocessor organizations, cache hierarchies and coherence protocols, thread-level speculation, and hardware and software reliability. He has a Ph.D. from Stanford University.
|09:40 - 10:15||Invited talk 1 : High Throughput Computing Data Center [pdf]|
|Jian Li, Huawei|
Abstract: Over years, data center (DC) technology has evolved from DC 1.0 (tightly-coupled silos) to DC 2.0 (computer virtualization) in order to enhance data processing capability. In the era of big data, highly diversified analytics applications continue to stress data center capacity. The mounting requirements on throughput, resource utilization, manageability and energy efficiency demand seamless integration of heterogeneous system resources to adapt to varied big data applications, for which DC 2.0 does not suffice. By rethinking of the challenges of big data applications, Huawei proposes a High Throughput Computing Data Center architecture (HTC-DC) toward the design of DC 3.0. HTC-DC features resource disaggregation via unified interconnection. It offers PB-level data processing capability, intelligent manageability, high scalability and high energy efficiency, hence a promising candidate for DC 3.0.
Bio: Jian Li is a research program director of big data and analytics at Huawei Technologies.Prior to that, he was a research scientist at IBM Austin research laboratory, an executive solution architect at IBM growth markets unit big data center of competency, and a chief architect of big data systems.He earned a Ph.D. degree in electrical and computer engineering from Cornell University.He also holds an adjunct position at the Texas A&M University.
|10:15 - 10:35||Coffee Break|
|10:35 - 12:00||Accelerating Big Data Processing (Session 1)|
Generalized Pattern Matching Micro-Engine
Yuanwei Fang (University of Chicago)
Raihan Rasool (King Faisal University)
Dilip Vasudevan (University of Chicago)
Andrew Chien (Argonne National Laboratory)
Resource Allocation for Hardware Implementations of Map
Richard Townsend (Columbia University)
Martha Kim (Columbia University)
Stephen Edwards (Columbia University)
GPUdrive: Reconsidering Storage Accesses for GPU Acceleration
Mustafa Shihab (The University of Texas at Dallas)
Karl Taht (The University of Texas at Dallas)
Myoungsoo Jung (The University of Texas at Dallas)
|12:00 - 13:10||Lunch Time|
|13:10 - 13:50||Invited talk 2 : Big vs. Small cores for Big Data [pdf]|
|Avi Mendelson, Technion - Israel Institute of Technology|
Bio: Avi Mendelson is a professor in the CS and EE departments Technion, Israel, and a member of the TCE (Technion Computer Engineering center). He earns his BSC and MSC degrees from the CS department, Technion, and got his PhD from University of Massachusetts at Amherst (UMASS).
Prof. Avi Mendelson has a blend of industrial and academic experience. As part of his industrial role, he spent 11 years in Intel, where he served as a senior researcher and Principle engineer in the Mobile Computer Architecture Group, in Haifa. While in Intel he was the chief architect of the CMP (multi-core-on-chip) feature of the first dual core processors Intel developed.
His research interests span over different areas such as Computer architecture, Operating systems, Power management, reliability, fault-tolerance, cloud computing, HPC and GPGPU.
Recently he served as the general manager of the ISCA-40 conference that was held in Tel-Aviv.
|13:50 - 15:10||Big Data Practice (Session 2)|
A Power Characterization and Management of GPU Graph Traversal
Adam McLaughlin (Georgia Institute of Technology)
Indrani Paul (AMD)
Joseph Greathouse (AMD)
Srilatha Manne (AMD)
Sudhakar Yalamanchili (Georgia Institute of Technology)
Performance Models of Access Latency in Cloud Storage Systems
Qiqi Shuai (The University of Hong Kong)
Victor.O.K. Li (The University of Hong Kong)
Yixuan Zhu (The University of Hong Kong)
GEMS: Graph database Engine for Multithreaded Systems
Alessandro Morari (Pacific Northwest National Laboratory)
Vito Giovanni Castellana (Pacific Northwest National Laboratory)
Oreste Villa (NVIDIA)
Antonino Tumeo (Pacific Northwest National Laboratory)
Jesse Weaver (Pacific Northwest National Laboratory)
David Haglin (Pacific Northwest National Laboratory)
Sutanay Choudhury (Pacific Northwest National Laboratory)
John Feo (Pacific Northwest National Laboratory)
|15:10 - 15:30||Coffee break|
|15:30 - 17:00||Panel : Architecture and System for Big Data (BD) Processing|
|Moderator: Jian Li (Huawei)|
| Boris Grot (Univ. of Edinburgh)|
| Avi Mendelson (Technion - Israel Institute of Technology)|
| Liang Peng (Huawei)|
| Josep Torrellas (UIUC)|
Lixin Zhang, ICT/CAS China
Xiufeng Sui, ICT/CAS China
Zhulin Wei, Huawei
Shujie Zhang, Huawei
Christos Kozyrakis, Stanford University USA
Yungang Bao, ICT/CAS China
Zhe Li, Huawei
Xi Tan, Huawei
Boris Grot,University of Edinburgh
Eric Chung,Microsoft Research
H. Peter Hofstee,IBM
Jishen Zhao,HP Lab
Jian Li, Huawei
Jichuan Chang, HP Labs
Evan Speight, IBM Research
Call for papers
The term "Big Data" refers to the continuing massive expansion in the data volume and diversity as well as the speed and complexity of data processing. The use of big data underpins critical activities in all sectors of our society. Achieving the full transformative potential of big data in this increasingly digital world requires both new data analysis algorithms and a new class of systems to handle the dramatic data growth, the demand to integrate structured and unstructured data analytics, and the increasing computing needs of massive-scale analytics.
We are pleased to request papers for presentation at the upcoming Fourth Workshop on Architectures and Systems for Big Data (ASBD 2014) held in conjunction with ISCA-41. The workshop will provide a forum to exchange research ideas related to all critical aspects of emerging analytics systems for big data, including architectural support, benchmarks and metrics, data management software, operating systems, and emerging challenges and opportunities. We hope to attract a group of interdisciplinary researchers from academia, industry and government research labs. To encourage discussion between participants, the workshop will include significant time for interactions between the presenters and the audience. We also plan to have a keynote speaker and/or panel session.
Topics of interest include but are not limited to:
Processor, memory and system architectures for data analytics
Benchmarks, metrics and workload characterization for big data
Accelerators for analytics and data-intensive computing
Implications of data analytics to mobile and embedded systems
Energy efficiency and energy-efficient designs for analytics
Availability, fault tolerance and data recovery in big data environments
Scalable system and network designs for high concurrency/bandwidth streaming
Data management and analytics for vast amounts of unstructured data
Evaluation tools, methodologies and workload synthesis
OS, distributed systems and system management support for large-scale analytics
Debugging and performance analysis tools for analytics and big data
Programming systems and language support for deep analytics
MapReduce and other processing paradigms for analytics
We encourage researchers from all institutions to submit their work for review. Preliminary results of interesting ideas and work-in-progress are welcome. Submissions that are likely to generate vigorous discussion will be favored!
Submission format: All papers should be submitted in PDF format,
using 10 point or larger font for text (8 points or larger for figures and
tables), total length not to exceed 6 pages.
Paper Submission : https://www.easychair.org/conferences/?conf=asbd2014
Submissions deadline: April 11, 2014
Author notification: April 30, 2014