Abstract: As we move to integration levels of 1,000-core processor chips, it is clear that energy and power consumption are the most formidable obstacles. To construct such a chip, we need to rethink the whole compute stack from the ground up for energy efficiency and attain Extreme-Scale Computing. First of all, we want to operate at low voltage, since this is the point of maximum energy efficiency. Unfortunately, in such an environment, we have to tackle substantial process variation. Hence, it is important to design efficient voltage regulation, so that each region of the chip can operate at the most efficient voltage and frequency point. At the architecture level, we require simple cores organized in a hierarchy of clusters. Moreover, we also need techniques to reduce the leakage of on-chip memories and to lower the voltage guardbands of logic. Finally, data movement should be minimized, through both hardware and software techniques. With a systematic approach that cuts across multiple layers of the computing stack, we can deliver the required energy efficiencies.

Bio: Josep Torrellas is a Professor of Computer Science and Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. He is a Fellow of IEEE and ACM. He is the Director of the Center for Programmable Extreme-Scale Computing, a center focused on architectures for extreme energy and power efficiency. He was until recently the  Director of the Intel-Illinois Parallelism Center (I2PC), a center created by Intel to advance parallel computing in clients. He has made contributions to parallel computer architecture in the areas of shared memory multiprocessor organizations, cache hierarchies and coherence protocols, thread-level speculation, and hardware and software reliability. He has a Ph.D. from Stanford University.

Abstract: Over years, data center (DC) technology has evolved from DC 1.0 (tightly-coupled silos) to DC 2.0 (computer virtualization) in order to enhance data processing capability. In the era of big data, highly diversified analytics applications continue to stress data center capacity. The mounting requirements on throughput, resource utilization, manageability and energy efficiency demand seamless integration of heterogeneous system resources to adapt to varied big data applications, for which DC 2.0 does not suffice. By rethinking of the challenges of big data applications, Huawei proposes a High Throughput Computing Data Center architecture (HTC-DC) toward the design of DC 3.0. HTC-DC features resource disaggregation via unified interconnection. It offers PB-level data processing capability, intelligent manageability, high scalability and high energy efficiency, hence a promising candidate for DC 3.0.

Bio: Jian Li is a research program director of big data and analytics at Huawei Technologies.Prior to that, he was a research scientist at IBM Austin research laboratory, an executive solution architect at IBM growth markets unit big data center of competency, and a chief architect of big data systems.He earned a Ph.D. degree in electrical and computer engineering from Cornell University.He also holds an adjunct position at the Texas A&M University.

Generalized Pattern Matching Micro-Engine
Yuanwei Fang (University of Chicago)
Raihan Rasool (King Faisal University)
Dilip Vasudevan (University of Chicago)
Andrew Chien (Argonne National Laboratory)

ASBD_slides_Fang.pdf

ASBD_paper_Fang.pdf

Resource Allocation for Hardware Implementations of Map
Richard Townsend (Columbia University)
Martha Kim (Columbia University)
Stephen Edwards (Columbia University)

ASBD_slides_Townsend.pdf

ASBD_paper_Townsend.pdf

GPUdrive: Reconsidering Storage Accesses for GPU Acceleration
Mustafa Shihab (The University of Texas at Dallas)
Karl Taht (The University of Texas at Dallas)
Myoungsoo Jung (The University of Texas at Dallas)

ASBD_slides_Shihab.pdf

ASBD_paper_Shihab.pdf

Bio: Avi Mendelson is a professor in the CS and EE departments Technion, Israel, and a member of the TCE (Technion Computer Engineering center). He earns his BSC and MSC degrees from the CS department, Technion, and got his PhD from University of Massachusetts at Amherst (UMASS).   Prof. Avi Mendelson has a blend of industrial and academic experience. As part of his industrial role, he spent 11 years in Intel, where he served as a senior researcher and Principle engineer in the Mobile Computer Architecture Group, in Haifa. While in Intel he was the chief architect of the CMP (multi-core-on-chip) feature of the first dual core processors Intel developed.  His research interests span over different areas such as Computer architecture, Operating systems, Power management, reliability, fault-tolerance, cloud computing, HPC and GPGPU.   Recently he served as the general manager of the ISCA-40 conference that was held in Tel-Aviv.

A Power Characterization and Management of GPU Graph Traversal 
Adam McLaughlin (Georgia Institute of Technology)
Indrani Paul (AMD)
Joseph Greathouse (AMD)
Srilatha Manne (AMD)
Sudhakar Yalamanchili (Georgia Institute of Technology)

ASBD_slides_McLaughlin.pdf

ASBD_paper_McLaughlin.pdf

Performance Models of Access Latency in Cloud Storage Systems
Qiqi Shuai (The University of Hong Kong)
Victor.O.K. Li (The University of Hong Kong)
Yixuan Zhu (The University of Hong Kong)

ASBD_Talk_Shuai.pdf

ASBD_paper_Shuai.pdf

GEMS: Graph database Engine for Multithreaded Systems
Alessandro Morari (Pacific Northwest National Laboratory)
Vito Giovanni Castellana (Pacific Northwest National Laboratory)
Oreste Villa (NVIDIA)
Antonino Tumeo (Pacific Northwest National Laboratory)
Jesse Weaver (Pacific Northwest National Laboratory)
David Haglin (Pacific Northwest National Laboratory)
Sutanay Choudhury (Pacific Northwest National Laboratory)
John Feo (Pacific Northwest National Laboratory)

ASBD_slides_Morari.pdf

ASBD_paper_Morari.pdf